An asynchronous fully digital delay locked loop for DDR SDRAM data recovery

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Delay Locked Loops (DLLs) have become a standard structure in IC design, providing programmable, calibrated on-chip delays. They can be used, for example, to deskew clocks by matching delay paths. One application is in data recovery from DDR SDRAMs whose data strobe edges need retarding to provide adequate setup times for latching read data. The DLL described here was developed as a solution to this problem. It is wholly amenable to implementation on a purely digital CMOS device using standard cells. The authors' background in self-timed circuits led to a novel, compact design - particularly in regard of the phase detector - which can have adjustable hysteresis to avoid jitter. The unit achieves lock rapidly and can subsequently track environmental variations without pausing operation for recalibration. It has been fabricated in 130 nm CMOS and is in use in a SoC SDRAM interface. © 2012 IEEE.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.
PublisherIEEE Computer Society
Pages49-56
Number of pages7
ISBN (Print)9780769546889
DOIs
Publication statusPublished - 2012
Event2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012 - Copenhagen
Event duration: 1 Jul 2012 → …

Conference

Conference2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012
CityCopenhagen
Period1/07/12 → …