A novel area-efficient binary adder

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Abstract

A novel circuit for binary addition based on a parallel-prefix carry structure is presented. This circuit uses a recoding of the conventional carry kill and generate terms to yield a number of improvements over previous designs. In particular, a single circuit produces both the carry signals and the Sum, Sum + 1 data that is required for a carry selection circuit, supporting a range of possible implementations all of which have high performance, regular layout and good area-efficiency. The simple design also leads to good power-efficiency. Binary adders based on this technique have been used in the ARM9TDMI, the ARM Piccolo DSP coprocessor, and the AMULET3 asynchronous ARM processor.

Bibliographical metadata

Original languageEnglish
Title of host publicationConference Record of the Asilomar Conference on Signals, Systems and Computers
Pages119-123
Number of pages5
Volume1
Publication statusPublished - 2000
Event34th Asilomar Conference - Pacific Grove, CA, United States
Event duration: 29 Oct 20001 Nov 2000

Conference

Conference34th Asilomar Conference
CountryUnited States
CityPacific Grove, CA
Period29/10/001/11/00