A High-Resolution CMOS Time to Digital Converter Utilising a Vernier Delay Line

Research output: Contribution to journalArticle

  • Authors:
  • P Dudek
  • S Szczepanski
  • J V Hatfield

Bibliographical metadata

Original languageEnglish
Pages (from-to)240-247
Number of pages8
JournalIEEE Journal of Solid State Circuits
Volume35
Issue number2
Publication statusPublished - Feb 2000