3-D multilayer monolithic integration of vertical-oriented double-heterojunction GaAs based pHEMT and thermal influence on device parameters

Research output: Contribution to journalArticle

Abstract

This study focuses on 3-D multilayer monolithic integration of vertical-oriented double-heterojunction AlGaAs/InGaAs/GaAs based pseudomorphic high electron mobility transistors. The effects of the presence of 3-D components above the active layer were accomplished by comparing three multilayer fabricated device of different thickness with a virgin device where the thickness of the 3-D components e.g., both metal and polyimide layer were varied. The output current, on-state gate leakage, transconductance are found to be decrease with the increase in thickness of the 3-D components and on the other hand, the on-state resistance, knee voltage and off-state gate leakage is increased. Lastly, the thermal influences on the device behaviour such as off-state and on-state gate leakage, barrier inhomogeneities at Schottky contacts, zero temperature coefficients at the transfer curve, and the threshold voltage as a function of drain bias were measured and analyzed for the both pre and post fabricated multilayer devices. These effective comparisons in terms of thickness and temperature of the both device are useful for future designs and optimizations of multilayer vertical stacked 3-D MMICs.

Bibliographical metadata

Original languageEnglish
Pages (from-to)24-30
Number of pages7
JournalSolid-State Electronics
Volume132
Early online date6 Mar 2017
DOIs
StatePublished - 1 Jun 2017