Advanced Processor Technology

Publications

  1. 1980
  2. Published

    MU6-G. A new design to achieve mainframe performance from a mini-sized computer

    Edwards, D. B. G., Knowles, A. E. & Woods, J. V., 6 May 1980, In: Proceedings - International Symposium on Computer Architecture. p. 161-167 7 p.

    Research output: Contribution to journalConference articlepeer-review

  3. 1992
  4. Published

    Register locking in an asynchronous microprocessor

    Paver, N. C., Day, P., Furber, S. B., Garside, J. D. & Woods, J. V., 15 Oct 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors. Cambridge, MA: IEEE, p. 351-355 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  5. 1993
  6. Published

    A CMOS VLSI Implementation of an Asynchronous ALU

    Garside, J. D., Furber, S. (ed.) & Edwards, M. (ed.), 1993, Asynchronous Design Methodologies. Furber, S. B. & Edwards, M. (eds.). Elsevier BV, Vol. A-28. p. 181-192 12 p. (IFIP Transactions).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  7. Published

    A micropipelined ARM

    Furber, S. B., Day, P., Garside, J. D., Paver, N. C., Woods, J. V., Yanagawa, K. (ed.) & Ivey, P. A. (ed.), 1993, VLSI. Yanagawa, K. & Ivey, P. A. (eds.). Elsevier BV, Vol. A-42. p. 211-220 10 p. (IFIP Transactions).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  8. Published

    Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993

    Furber, S. B. (ed.) & Edwards, M. (ed.), 1993, IFIP Transactions. Elsevier BV, Vol. A-28. (IFIP Transactions).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  9. 1994
  10. Published

    AMULET1: A Micropipelined ARM

    Furber, S. B., Day, P., Garside, J. D., Paver, N. C. & Woods, J. V., 1994, COMPCON. p. 476-485 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  11. Published

    Micropipelined ARM

    Furber, S. B., Day, P., Garside, J. D., Paver, N. C. & Woods, J. V., 1994, Elsevier BV. 10 p.

    Research output: Book/ReportBookpeer-review

  12. Published

    The Design and Evaluation of an Asynchronous Microprocessor

    Furber, S. B., Day, P., Garside, J. D., Paver, N. C., Temple, S. & Woods, J. V., 1994, ICCD. IEEE Computer Society , p. 217-220 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  13. 1995
  14. Published

    Scan testing of asynchronous sequential circuits

    Petlin, O. A. & Furber, S. B., 1995, Proceedings of the IEEE Great Lakes Symposium on VLSI|Proc IEEE Great Lakes Symp VLSI. Los Alamitos, CA, United States: IEEE, p. 224-229 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  15. Published

    Scan testing of micropipelines

    Petlin, O. A. & Furber, S. B., 1995, Proceedings of the IEEE VLSI Test Symposium|Proc IEEE VLSI Test Symp. IEEE Computer Society , p. 296-301 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  16. Published

    Designing asynchronous sequential circuits for random pattern testability

    Petlin, O. A., Furber, S. B., Romankevich, A. M. & Groll, V. V., Jul 1995, In: IEE Proceedings: Computers and Digital Techniques. 142, 4, p. 299-305 7 p.

    Research output: Contribution to journalArticlepeer-review

  17. 1996
  18. Published

    Breaking step - The return of asynchronous logic

    Furber, S. B., 1996, IEE Colloquium (Digest)|IEE Colloq Dig. IEEE Computer Society , p. 1/4

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  19. Published

    Design for testability of an asynchronous adder

    Petlin, O. A., Farnsworth, C. & Furber, S. B., 1996, In: IEE Colloquium (Digest). 40

    Research output: Contribution to journalArticlepeer-review

  20. Published

    Four-phase micropipeline latch control circuits

    Furber, S. B. & Day, P., 1996, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 4, 2, p. 247-253 6 p.

    Research output: Contribution to journalArticlepeer-review

  21. Published

    Return of asynchronous logic

    Furber, S. B., 1996, IEEE International Test Conference (TC). IEEE, p. 938 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  22. Published

    MSH2 Sequence Variations and Inherited Colorectal Cancer Susceptibility

    Froggatt, N. J., Joyce, J. A., Evans, D. G. R., Lunt, P. W., Koch, D. J., Ponder, B. J. & Maher, E. R., 1 Jan 1996, In: European Journal of Cancer. 32A, 1, p. 178 1 p.

    Research output: Contribution to journalLetterpeer-review

  23. 1997
  24. Published

    AMULET 1: An asynchronous ARM microprocessor

    Woods, J. V., Day, P., Furber, S. B., Garside, J. D., Paver, N. C. & Temple, S., 1997, In: IEEE Transactions on Computers. 46, 4, p. 385-398 14 p.

    Research output: Contribution to journalArticlepeer-review

  25. Published

    AMULET1: A Asynchronous ARM Microprocessor

    Woods, J. V., Day, P., Furber, S. B., Garside, J. D., Paver, N. C. & Temple, S., 1997, In: IEEE Trans. Computers. 46, 4, p. 385-398 14 p.

    Research output: Contribution to journalArticle

  26. Published

    AMULET2e: An asynchronous embedded controller

    Furber, S. B., Garside, J. D., Temple, S., Liu, J., Day, P. & Paver, N. C., 1997, Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems|Proc Int Symp Adv Res Asynchr Circuits Syst. Anon (ed.). Los Alamitos, CA, United States: IEEE, p. 290-299 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  27. Published

    Built-in self-testing of micropipelines

    Petlin, O. A. & Furber, S. B., 1997, Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems|Proc Int Symp Adv Res Asynchr Circuits Syst. Anon (ed.). Los Alamitos, CA, United States: IEEE, p. 22-29 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  28. 1998
  29. Published

    AMULET3: a high-performance self-timed ARM microprocessor

    Furber, S. B., Garside, J. D. & Gilbert, D. A., 1998, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, p. 247-252 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  30. Published

    Asynchronous embedded control

    Furber, S. B., Garside, J. D., Temple, S., Day, P. & Paver, N. C., 1998, In: Integrated Computer-Aided Engineering. 5, 1, p. 57-68 12 p.

    Research output: Contribution to journalArticlepeer-review

  31. Published

    Asynchronous Macrocell Interconnect using MARBLE

    Bainbridge, W. J. & Furber, S. B., 1998, ASYNC. IEEE Computer Society , p. 122-132 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  32. Published

    Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language

    Endecott, P., Furber, S. B., Zobel, R. N. (ed.) & Möller, D. P. F. (ed.), 1998, ESM. Zobel, R. N. & Möller, D. P. F. (eds.). SCS Europe BVBA, p. 39-43 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  33. Published

    The design of an asynchronous VHDL synthesizer

    Tan, S. Y., Furber, S. B. & Yen, W. F., 1998, Proceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE. IEEE Computer Society , p. 44-51 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  34. Published

    System and method for real-time screening and routing of telephone calls

    Goodacre, AJ. & Prisock, JH., 13 Oct 1998, Patent No. 5822416

    Research output: Patent

  35. 1999
  36. Published

    AMULET2e: An asynchronous embedded controller

    Furber, S. B., Garside, J. D., Riocreux, P., Temple, S., Day, P., Liu, J. & Paver, N. C., 1999, In: Institute of Electrical and Electronics Engineers. Proceedings . 87, 2, p. 243-256 14 p.

    Research output: Contribution to journalArticlepeer-review

  37. Published

    AMULET3 revealed

    Garside, J. D., Furber, S. B. & Chung, S. H., 1999, Proceedings - International Symposium on Asynchronous Circuits and Systems. IEEE Computer Society , p. 51-59 9 p. 761522

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  38. 2000
  39. Published

    A novel area-efficient binary adder

    Furber, S. B. & Liu, J., 2000, Conference Record of the Asilomar Conference on Signals, Systems and Computers. Vol. 1. p. 119-123 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  40. Published

    AMULET3: A 100 MIPS asynchronous embedded processor

    Furber, S. B., Edwards, D. A. & Garside, J. D., 2000, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|Proc IEEE Int Conf Comput Des VLSI Comput Process. Piscataway, NJ, United States: IEEE, p. 329-334 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  41. Published

    AMULET3i - An asynchronous system-on-chip

    Garside, J. D., Bainbridge, W. J., Bardsley, A., Clark, D. M., Edwards, D. A., Furber, S. B., Liu, J., Lloyd, D. W., Mohammadi, S., Pepper, J. S., Petlin, O., Temple, S. & Woods, J. V., 2000, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEEE Computer Society , p. 162-175 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  42. Published

    On-chip timing reference for self-timed microprocessor

    Temple, S. & Furber, S. B., 25 May 2000, In: Electronics Letters. 36, 11, p. 942-943 2 p.

    Research output: Contribution to journalArticlepeer-review

  43. Published

    MARBLE: An asynchronous on-chip macrocell bus

    Bainbridge, W. J. & Furber, S. B., 1 Aug 2000, In: Microprocessors and Microsystems. 24, 4, p. 213-222 10 p.

    Research output: Contribution to journalArticlepeer-review

  44. 2001
  45. Published

    Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

    Bainbridge, W. J. & Furber, S. B., 2001, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEEE Computer Society , p. 118-126 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  46. Published

    Processors

    Garside, J. D., Sparsø, J. (ed.) & Furber, S. (ed.), 2001, Principles of Asynchronous Circuit Design - A Systems Perspective. Kluwer Academic Publishers

    Research output: Chapter in Book/Report/Conference proceedingChapter

  47. Published

    Applying asynchronous techniques to a vtterbi decoder design

    Brackenbury, L. E. M., Cumpstey, M., Furber, S. B. & Riocreux, P. A., 19 Jan 2001, In: IEE Colloquium (Digest). 42, p. 7-11 5 p.

    Research output: Contribution to journalArticlepeer-review

  48. Published

    Power management in the amulet microprocessors

    Furber, S. B., Efthymiou, A., Garside, J. D., Lloyd, D. W., Lewis, M. J. G. & Temple, S., Mar 2001, In: IEEE Design and Test of Computers. 18, 2, p. 42-51 9 p.

    Research output: Contribution to journalArticlepeer-review

  49. 2002
  50. Published

    Validating the AMULET microprocessors

    Furber, S., 2002, In: Computer Journal. 45, 1, p. 19-26 7 p.

    Research output: Contribution to journalArticlepeer-review

  51. Published

    Chain: A delay-insensitive chip area interconnect

    Bainbridge, J. & Furber, S., Sep 2002, In: IEEE Micro. 22, 5, p. 16-23 7 p.

    Research output: Contribution to journalArticlepeer-review

  52. Published

    An Asynchronous Victim Cache

    Hormdee, D., Garside, J. & Furber, S. B., 1 Sep 2002, Proceedings Euromicro Symposium on Digital System Design. IEEE Computer Society , p. 4-11 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  53. 2003
  54. Published

    An asynchronous low latency arbiter for Quality of Service (QoS) applications

    Felicijan, T., Bainbridge, W. & Furber, S., 2003, Proceedings of the International Conference on Microelectronics, ICM. IEEE, Vol. 2003-January. p. 123-126 4 p. 1287737

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  55. Published

    An investigation into the security of self-timed circuits

    Yu, Z. C., Furber, S. B. & Plana, L. A., 2003, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEEE Computer Society , p. 206-215 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  56. Published

    Delay-insensitive, point-to-point interconnect using M-of-N codes

    Bainbridge, W. J., Toms, W. B., Edwards, D. A. & Furber, S. B., 2003, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. p. 132-140 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  57. Published

    The ARM Multiprocessor Architecture

    Goodacre, J., 2003, host publication: MPSoc .

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  58. Published

    Understanding the Options for Embedded Multiprocessing

    Goodacre, J., 2003, In: ARM Information Quarterly. 2, 2, p. 33-39

    Research output: Contribution to journalArticlepeer-review

  59. Published

    Designing robust asynchronous circuit components

    Mohammadi, S., Furber, S. & Garside, J., Jun 2003, In: IEE Proceedings: Circuits, Devices and Systems. 150, 3, p. 161-166 5 p.

    Research output: Contribution to journalArticlepeer-review

  60. Published

    Microprocessors and Microsystems: Editorial

    Furber, S., Oct 2003, In: Microprocessors and Microsystems. 27, 9, p. 407-408 1 p.

    Research output: Contribution to journalArticlepeer-review

  61. Published

    An asynchronous copy-back cache architecture

    Hormdee, D., Garside, J. D. & Furber, S. B., 3 Nov 2003, In: Microprocessors and Microsystems. 27, 10, p. 485-500 15 p.

    Research output: Contribution to journalArticlepeer-review

  62. Published

    An asynchronous ternary logic signaling system

    Felicijian, T. & Furber, S. B., Dec 2003, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11, 6, p. 1114-1119 5 p.

    Research output: Contribution to journalArticlepeer-review

  63. 2004
  64. Published

    An asynchronous on-chip network router with Quality-of-Service (QoS) support

    Felicijan, T. & Furber, S. B., 2004, Proceedings - IEEE International SOC Conference. Chickanosky, J., Ha, D. & Auletta, R. (eds.). p. 274-277 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  65. Published

    ARM tries multiprocessors for faster consumer devices

    Goodacre, J., 2004, In: Electronics Systems and Software. 2, 3, p. 46

    Research output: Contribution to journalArticlepeer-review

  66. Published

    Minimizing the power consumption of an asynchronous multiplier

    Liu, Y. & Furber, S., 2004, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.. Springer Nature, Vol. 3254. p. 289-300 11 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  67. Published

    The Design of a Low Power Asynchronous Multiplier

    Liu, Y. & Furber, S., 2004, Proceedings of the International Symposium on Low Power Electronics and Design. January ed. IEEE, Vol. 2004-January. p. 301-306 6 p. 1349355

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  68. Published

    The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip

    Bainbridge, W. J., Plana, L. A. & Furber, S. B., Feb 2004, Proceedings - Design, Automation and Test in Europe Conference and Exhibition. Lindwer, M., Gerousis, V. & Fifueras, J. (eds.). IEEE Computer Society , Vol. 3. p. 274-279 6 p. 1269249

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  69. Published

    Power control within a coherent multi-processing system

    Goodacre, A., Pruvost, J-A., Piry, F., Lataille, N. & Grandou, G., 30 Mar 2004

    Research output: Patent

  70. Published

    Design and analysis of a self-timed duplex communication system

    Yakovlev, A., Furber, S., Krenz, R. & Bystrov, A., Jul 2004, In: IEEE Transactions on Computers. 53, 7, p. 798-814 16 p.

    Research output: Contribution to journalArticlepeer-review

  71. Published

    Challenges in programming multiprocessor platforms

    Goodacre, J., 5 Jul 2004, host publication. ARM Ltd

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  72. Published

    Sparse distributed memory using N-of-M codes

    Furber, S. B., John Bainbridge, W., Mike Cumpstey, J. & Temple, S., Dec 2004, In: Neural Networks. 17, 10, p. 1437-1451 14 p.

    Research output: Contribution to journalArticlepeer-review

  73. 2005
  74. Published

    A low power embedded dataflow coprocessor

    Liu, Y. & Furber, S., 2005, Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI|Proc. IEEE Comput. Soc. Annu. Symp. VLSI New Frontiers VLSI Design. Smailagic, A. & Ranganathan, N. (eds.). IEEE Computer Society , p. 246-247 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  75. Published

    A spiking neural sparse distributed memory implementation for learning and predicting temporal sequences

    Bose, J., Furber, S. B. & Shapiro, J. L., 2005, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.. Springer Nature, Vol. 3696. p. 115-120 5 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  76. Published

    An associative memory for the on-line recognition and prediction of temporal sequences

    Bose, J., Furber, S. B. & Shapiro, J. L., 2005, Proceedings of the International Joint Conference on Neural Networks (IJCNN) 2005 : July 31 - August 4, 2005, Hilton Montréal Bonaventure Hotel, Montréal, Québec, Canada. IEEE, Vol. 2. p. 1223-1228 5 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

  77. Published

    Future trends in SoC interconnect

    Furber, S., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). Vol. 2005. p. 295-298 4 p. 1500079

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  78. Published

    Future trends in SoC interconnect

    Furber, S. & Bainbridge, J., 2005, 2005 International Symposium on System-on-Chip, Proceedings. Vol. 2005. p. 183-186 4 p. 1595673

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  79. Published

    Measuring SMP

    Goodacre, J., 2005, host publication. MPSoc

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  80. Published

    The design of an asynchronous carry-lookahead adder based on data characteristics

    Liu, Y. & Furber, S., 2005, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.. Springer Nature, Vol. 3728. p. 647-656 9 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  81. Published

    Parallelism and the ARM instruction set architecture

    Goodacre, J. & Sloss, AN., Jul 2005, In: Computer (New York). 38, 7, p. 42-50 8 p.

    Research output: Contribution to journalArticlepeer-review

  82. Published

    Multiprocessing: The race continues

    Goodacre, J., Oct 2005, In: Electronic Product Design. 26, 10, p. 9-10

    Research output: Contribution to journalArticlepeer-review

  83. 2006
  84. Published

    A system for transmitting a coherent burst of activity through a network of spiking neurons

    Bose, J., Furber, S. B. & Shapiro, J. L., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.. Springer Nature, Vol. 3931. p. 44-48 4 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  85. Published

    High-performance computing for systems of spiking neurons

    Furber, S. B., Temple, S. & Brown, A., 2006, Proceedings of AISB'06: Adaptation in Artificial and Biological Systems. Vol. 2. p. 29-36 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  86. Published

    Living with failure: Lessons from nature?

    Furber, S., 2006, Proceedings - Eleventh IEEE European Test Symposium, ETS 2006|Proc. Eleventh IEEE Eur. Test Symp.. IEEE Computer Society , Vol. 2006. p. 4-5 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  87. Published

    Multiprocessing design choices: multi-processor or multi-threading technology

    Goodacre, J., 2006, In: Electronic Design and Application. 8, 34 p.

    Research output: Contribution to journalArticlepeer-review

  88. Published

    On-chip and inter-chip networks for modeling large-scale neural systems

    Furber, S. B., Temple, S. & Brown, A. D., 2006, ISCAS. IEEE

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  89. Published

    On-chip and inter-chip networks for modelling large-scale neural systems

    Furber, S. B., Temple, S. & Brown, A., 2006, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1945-1948 4 p. 1692992

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  90. Published

    Preventing denial-of-service attacks in shared CMP caches

    Keramidas, G., Petoumenos, P., Kaxiras, S., Antonopoulos, A. & Serpanos, D., 2006, Embedded computer systems: architectures, modeling, and simulation: 6th international workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006 proceedings. Vassiliadis, S., Wong, S. & Hämäläinen, T. D. (eds.). Berlin, Heidelberg, New York: Springer Nature, p. 359-372 14 p. (Lecture notes in computer science; vol. 4017).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  91. Published

    Scalable Processing through Software Threading

    Goodacre, J., 2006, host publication. MPSoc

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  92. Published

    The design of a dataflow coprocessor for low power embedded hierarchical processing

    Liu, Y., Furber, S. & Li, Z., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.. Springer Nature, Vol. 4148. p. 425-438 13 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  93. Published

    Modeling cache sharing on chip multiprocessor architectures

    Petoumenos, P., Keramidas, G., Zeffer, H., Kaxiras, S. & Hagersten, E., 1 Dec 2006, Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006. IEEE, p. 160-171 12 p. 4086144

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  94. 2007
  95. Published

    ARM MPCore; The streamlined and scalable ARM11 processor core

    Hirata, K. & Goodacre, J., 2007, host publication. IEEE, p. 747-748 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  96. Published

    Asynchronous and self-timed processor design

    Garside, J. & Furber, S., 2007, Processor Design: System-on-Chip Computing for ASICs and FPGAs|Proc. Des.: System-on-Chip Comp. for ASICs and FPGAs. Springer Nature, p. 367-389 22 p.

    Research output: Chapter in Book/Report/Conference proceedingChapter

  97. Published

    Cache replacement based on reuse-distance prediction

    Keramidas, G., Petoumenos, P. & Kaxiras, S., 2007, 2007 25th international conference on computer design. IEEE, p. 245-250 6 p. 4601909

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  98. Published

    Extending the Cortex ARM version-7 architecture for next generation multicore

    Goodacre, J., 2007, host publication: MPSoc .

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  99. Published

    Maximising information recovery from rank-order codes

    Sen, B. & Furber, S. B., 2007, Proceedings of SPIE - The International Society for Optical Engineering. Vol. 6570. 65700C

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  100. Published

    Maximising information recovery from rank-order codes - art. no. 65700C

    Sen, B., Furber, S. & Dasarathy, B. V. (ed.), 2007, Conference on Data Mining, Intrusion Detection, Information Assurance and Data Networks Security 2007. Dasarathy, B. V. (ed.). SPIE, Vol. 6570. p. C5700-C5700

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  101. Published

    Notes on pulse signaling

    Ebergen, J., Furber, S., Saifhashemi, A., Nissar, N. & Chow, A., 2007, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEEE Computer Society , p. 15-24 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  102. Published

    Neural systems engineering

    Furber, S. & Temple, S., 22 Apr 2007, In: Journal of the Royal Society Interface. 4, 13, p. 193-206 13 p.

    Research output: Contribution to journalArticlepeer-review

  103. Published

    Sparse distributed memory using rank-order neural codes

    Furber, S. B., Brown, G., Bose, J., Cumpstey, J. M., Marshall, P. & Shapiro, J. L., May 2007, In: IEEE Transactions on Neural Networks. 18, 3, p. 648-659 11 p.

    Research output: Contribution to journalArticlepeer-review

  104. Published

    A GALS infrastructure for a massively parallel multiprocessor

    Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J. & Yang, S., Sep 2007, In: IEEE Design and Test of Computers. 24, 5, p. 454-463 9 p.

    Research output: Contribution to journalArticlepeer-review

  105. Published

    Mighty Multicore

    Goodacre, J. & Pitcher, G., Oct 2007, In: News Electronics. p. 29-30

    Research output: Contribution to journalArticlepeer-review

  106. Published

    Multicore processing for automotive applications

    Goodacre, J., Dec 2007, In: ATZ Elektronik Worldwide . 2, 4, p. 16-18 2 p.

    Research output: Contribution to journalArticlepeer-review

  107. Published

    Using value locality to reduce memory encryption overhead in embedded processors

    Keramidas, G., Petoumenos, P., Antonopoulos, A., Kaxiras, S. & Serpanos, D. N., 1 Dec 2007, 12th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2007 Proceedings. p. 632-637 6 p. 4416828. (IEEE International Conference on Emerging Technologies and Factory Automation, ETFA).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  108. 2008
  109. Published

    An admission control system for QoS provision on a best-effort GALS interconnect

    Yang, S., Furber, S. B., Shi, Y. & Plana, L. A., 2008, Proceedings - International Conference on Application of Concurrency to System Design, ACSD|Proc. Int. Conf. Appl. Concurrency Syst. Des. ACSD. IEEE, p. 200-207 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  110. Published

    An on-chip and inter-chip communications network for the SpiNNaker Massively-Parallel Neural Net Simulator

    Plana, L. A., Bainbridge, J., Furber, S., Salisbury, S., Shi, Y. & Wu, J., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008|Proc. IEEE Int. Symp. Netw. Chip NOCS. p. 215-216 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  111. Published

    Efficient modelling of spiking neural networks on a scalable chip multiprocessor

    Jin, X., Furber, S. B. & Woods, J. V., 2008, Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE, p. 2812-2819 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  112. Published

    Neural systems engineering

    Furber, S. & Temple, S., 2008, Studies in Computational Intelligence|Stud. Comput. Intell.. Springer Nature, Vol. 115. p. 763-796 33 p. (Studies in Computational Intelligence; vol. 115).

    Research output: Chapter in Book/Report/Conference proceedingChapter

  113. Published

    SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor

    Khan, M. M., Lester, D. R., Plana, L. A., Rast, A., Jin, X., Painkras, E. & Furber, S. B., 2008, Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE Computer Society , p. 2849-2856 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  114. Published

    Temporal Adaptation -- asynchronicity in processor design

    Furber, S., Garside, J. D., Wang, A. (ed.) & Naffziger, S. (ed.), 2008, Adaptive Techniques for Dynamic Processor Optimization Adaptive Techniques for Dynamic Processor Optimization Theory and Practice. Springer Nature, p. 229-247 19 p.

    Research output: Chapter in Book/Report/Conference proceedingChapter

  115. Published

    The Effect and Technique of System Coherence in ARM Multicore Technology

    Goodacre, J., 2008, host publication. MPSoc

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  116. Published

    The machinations of the mind [brain models]

    Furber, S., 2008, In: Engineering and Technology. 3, 5, p. 36-39 4 p.

    Research output: Contribution to journalArticlepeer-review

  117. Published

    Virtual synaptic interconnect using an asynchronous network-on-chip

    Rast, A. D., Yang, S., Khan, M. & Furber, S. B., 2008, Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE, p. 2727-2734 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  118. Published

    Future Architecture of MPSoC Platforms

    Goodacre, J., 16 Jun 2008, host publication. MPSoc

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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