Advanced Processor Technology
Publications
- Conference article › Research › Peer-reviewed
- Published
MU6-G. A new design to achieve mainframe performance from a mini-sized computer
Edwards, D. B. G., Knowles, A. E. & Woods, J. V., 6 May 1980, In: Proceedings - International Symposium on Computer Architecture. p. 161-167 7 p.Research output: Contribution to journal › Conference article › peer-review
- Software › Research
- Published
SpiNNaker 1M
Furber, S., Rhodes, O., Garside, J. & Lester, D., 1 Sep 2019Research output: Non-textual form › Software
- Working paper › Research
- Published
Fuse: Accurate Multiplexing of Hardware Performance Counters Across Executions
Neill, R., Drebes, A. & Pop, A., 2017, 25 p.Research output: Working paper
- Commissioned report › Research › Not peer-reviewed
- Published
Low Power Processing: Use Only the Power Needed to Get the Job Done
Goodacre, J., Dec 2008, ARM Ltd.Research output: Book/Report › Commissioned report
- Published
System Level Benchmarking Analysis of the Cortex-A9 MPCore
Goodacre, J. & Mijat, R., 2009, ARM Ltd.Research output: Book/Report › Commissioned report
- Published
Technology Preview: The ARMv8 Architecture
Goodacre, J., Nov 2011, ARM Ltd. 10 p.Research output: Book/Report › Commissioned report
- Scholarly edition › Research › Peer-reviewed
- Published
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
Koch, D., Hannig, F. & Ziener, D., 1 Sep 2015, 2 ed. http://arxiv.org/html/1508.06320.Research output: Book/Report › Scholarly edition › peer-review
- Anthology › Research › Peer-reviewed
- Published
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
Koch, D., Hannig, F. & Ziener, D., Sep 2014, 2014 ed. No publisher name. (FSP 2014)Research output: Book/Report › Anthology › peer-review
- Book › Research › Peer-reviewed
- Published
Micropipelined ARM
Furber, S. B., Day, P., Garside, J. D., Paver, N. C. & Woods, J. V., 1994, Elsevier BV. 10 p.Research output: Book/Report › Book › peer-review
- Published
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
Koch, D., Hannig, F. & Ziener, D., 1 Sep 2014, 1 ed. http://arxiv.org/html/1408.4423. (Proceedings of the International Workshop on FPGAs for Software Programmers (FSP))Research output: Book/Report › Book › peer-review
- Book › Research › Not peer-reviewed
- Published
El algoritmo de sintonización simple de controladores difusos: (ASSCD)
Gomez-Ramirez, E., Cortes Rios, J. C., Ortiz-De-La-Vega, H. A., Melin-Olmeda, E. P. & Castillo-Lopez, O., Sep 2017, Mexico: De La Salle Ediciones. 116 p.Research output: Book/Report › Book
- Published
Flash Memory Integration: Performance and Energy Considerations
Boukhobza, J. & Olivier, P., 6 Mar 2017, ISTE Press Ltd. 266 p.Research output: Book/Report › Book
- Published
FPGAs for Software Programmers
Koch, D. (ed.), Hannig, F. (ed.) & Ziener, D. (ed.), 2016, Springer Nature. 331 p.Research output: Book/Report › Book
- Published
SpiNNaker: A spiking neural network architecture
Furber, S. (ed.) & Bogdan, P. (ed.), 31 Mar 2020, Boston-Delpht: Now Publishers Inc. 350 p.Research output: Book/Report › Book
- Patent › Research
- Published
3D Interconected Die Stack
Goodacre, A., 13 May 2020, Patent No. GB2565310A, 8 Aug 2017Research output: Patent
- Published
Multi-processing system with coherent and non-coherent modes
Goodacre, A. J. & Piry, F. C. M., 16 Jun 2009, Patent No. 7549024Research output: Patent
- Published
Outputting dynamic local content on mobile devices
Goodacre, A. J., Merrick, B. & Hitchman, D., 29 Dec 2009, Patent No. 7640491Research output: Patent
- Published
Power control within a coherent multi-processing system
Goodacre, A., Pruvost, J-A., Piry, F., Lataille, N. & Grandou, G., 30 Mar 2004Research output: Patent
- Published
System and method for real-time screening and routing of telephone calls
Goodacre, AJ. & Prisock, JH., 13 Oct 1998, Patent No. 5822416Research output: Patent
- Published
Virtualisation supporting guest operating systems using memory protection units
Goodacre, A. J., 3 Dec 2015, Patent No. US20150347052 A1, Priority date 5 Feb 2013Research output: Patent
- Abstract › Research › Peer-reviewed
- Accepted/In press
A Self-Compilation Flow Demo on FOS – the FPGA Operating System
Pham, K., Vaishnav, A., Powell, J. & Koch, D., 2020, (Accepted/In press).Research output: Contribution to conference › Abstract › peer-review
- Published
Event-based computation: Unsupervised elementary motion decomposition
Bogdan, P., Pineda Garcia, G., Davidson, S., Hopkins, M., James, R. & Furber, S., 2019, p. 20-23. 4 p.Research output: Contribution to conference › Abstract › peer-review
- Poster › Research › Peer-reviewed
- Accepted/In press
Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs
Pavlidis, V. & Mihajlovic, M., 8 Nov 2018, (Accepted/In press).Research output: Contribution to conference › Poster › peer-review
- Accepted/In press
Adaptive Word Reordering for Low-Power Inter-Chip Communication
Maragkoudaki, E., Mroszczyk, P. & Pavlidis, V., 8 Nov 2018, (Accepted/In press).Research output: Contribution to conference › Poster › peer-review
- Published
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems
Höppner, S., Yan, Y., Vogginger, B., Dixius, A., Partzsch, J., Joshi, P., Neumärker, F., Hartmann, S., Schiefer, S., Scholze, S., Ellguth, G., Cederstroem, L., Eberlein, M., Mayr, C., Temple, S., Plana, L. A., Garside, J., Davidson, S., Lester, D. & Furber, S., 2017.Research output: Contribution to conference › Poster › peer-review
- Published
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems
Partzsch, J., Mayr, C., Vogginger, B., Schuffny, R., Rast, A., Plana, L. & Furber, S., 2013.Research output: Contribution to conference › Poster › peer-review
- Published
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
Yousefzadeh, A., Jabłoński, M., Iakymchuk, T., Linares-Barranco, A., Rosado, A., Plana, L. A., Serrano-Gotarredona, T., Furber, S. & Linares-Barranco, B., 2017.Research output: Contribution to conference › Poster › peer-review
- Accepted/In press
Metal Stack and Partitioning Exploration for Monolithic 3D ICs
Sketopoulos, N., Sotiriou, C. & Pavlidis, V., 11 May 2020, (Accepted/In press).Research output: Contribution to conference › Poster › peer-review
- Accepted/In press
PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
Maragos, K., Lentaris, G., Soudris, D. & Pavlidis, V., 15 Nov 2018, (Accepted/In press).Research output: Contribution to conference › Poster › peer-review
- Accepted/In press
STA Compatible Backend Design Flow for TSV-based 3-D ICs
Kalargaris, C., Chen, Y-C. & Pavlidis, V., 5 Dec 2017, (Accepted/In press). 6 p.Research output: Contribution to conference › Poster › peer-review
- Accepted/In press
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength
Wang, W., Pavlidis, V. & Cheng, Y., 12 May 2020, (Accepted/In press).Research output: Contribution to conference › Poster › peer-review
- Poster › Research › Not peer-reviewed
- Published
Live Demonstration: Handwritten Digit Recognition Using Spiking Deep Belief Networks on SpiNNaker
Stromatias, E., Neil, D., Galluppi, F., Pfeiffer, M., Liu, S-C. & Furber, S., 2015.Research output: Contribution to conference › Poster
- Paper › Research › Peer-reviewed
- Published
ACTiCLOUD: Enabling the Next Generation of Cloud Applications
Goodacre, A., 17 Jul 2017.Research output: Contribution to conference › Paper › peer-review
- Accepted/In press
Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units
Paraskevas, K., Iordanou, K., Luján, M. & Goodacre, J., 2020, (Accepted/In press). 11 p.Research output: Contribution to conference › Paper › peer-review
- Published
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip
Mikaitis, M., Lester, D., Shang, D., Furber, S., Liu, G., Garside, J., Scholze, S., Hoppner, S. & Dixius, A., 17 Sep 2018, p. 37-44. 8 p.Research output: Contribution to conference › Paper › peer-review
- Published
BITMAN: A tool and API for FPGA bitstream manipulations
Pham, K., Horta, E. & Koch, D., 2017.Research output: Contribution to conference › Paper › peer-review
- Accepted/In press
Challenges and proposals for enabling dynamic heterogeneous execution of Big Data frameworks
Xekalaki, M., Fumero Alfonso, J. & Kotselidis, C-E., 31 Oct 2018, (Accepted/In press).Research output: Contribution to conference › Paper › peer-review
- Accepted/In press
Cost Modeling and Analysis of TSV and Contactless 3D-ICs
Jiang, M., Papistas, I. & Pavlidis, V., 13 May 2020, (Accepted/In press).Research output: Contribution to conference › Paper › peer-review
- Accepted/In press
Cross-ISA Debugging in Meta-circular VMs
Kotselidis, C., Nisbet, A., Zakkak, F. & Foutris, N., 6 Oct 2017, (Accepted/In press).Research output: Contribution to conference › Paper › peer-review
- Published
Demystifying Crypto-Mining: Analysis and Optimizations of memory-hard PoW Algorithms
Han, R., Foutris, N. & Kotselidis, C., 2019, p. 1-12. 12 p.Research output: Contribution to conference › Paper › peer-review
- Published
Enabling RISC-V support on MaxineVM
Zakkak, F., Fumero, J. & Kotselidis, C., 7 May 2018.Research output: Contribution to conference › Paper › peer-review
- Accepted/In press
Large Utility Sorting on FPGAs
Manev, K. & Koch, D., 16 Sep 2018, (Accepted/In press).Research output: Contribution to conference › Paper › peer-review
- Published
Objective assessment of Asthenia using energy and low-to-high spectral ratio
Jalalinajafabadi, F., Gadepalli, C., Ghasempour, M., Ascott, F., Luján, M., Homer, J. & Cheetham, B., Jul 2015, p. 76-83.Research output: Contribution to conference › Paper › peer-review
- Published
Optimized Task Graph Mapping on a Many-core Neuromorphic Supercomputer
Sugiarto, I., Campos, P., Dahir, N., Tempesti, G. & Furber, S., 14 Sep 2017. 6 p.Research output: Contribution to conference › Paper › peer-review
- Published
Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach
Goodacre, A., 30 Aug 2017.Research output: Contribution to conference › Paper › peer-review
DOI: 10.1109/DSD.2017.37 - Published
Performance Analysis for Languages Hosted on the Truffle Framework
Gaikwad, S., Nisbet, A. & Luján, M., 2018.Research output: Contribution to conference › Paper › peer-review
- Published
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker
Yousefzadeh, A., Soto, M., Serrano-gotarredona, T., Galluppi, F., Plana, L., Furber, S. & Linares-barranco, B., May 2018, p. 1-4.Research output: Contribution to conference › Paper › peer-review
- Published
Profiling a Many-core Neuromorphic Platform
Sugiarto, I., Plana, L. A., Temple, S., Sen Bhattacharya, B., Furber, S. & Camilleri, P., 21 Sep 2017. 6 p.Research output: Contribution to conference › Paper › peer-review
- Published
Profiling and Tracing Support for Java Applications
Nisbet, A., Nobre, N. M., Riley, G. & Luján, M., 11 Apr 2019, p. 1. 8 p.Research output: Contribution to conference › Paper › peer-review
- Published
Quantitative Validation of Physically Based Deformable Models in Computer Graphics
Banks, M., Hazel, A. & Riley, G., 16 Apr 2018. 10 p.Research output: Contribution to conference › Paper › peer-review