Advanced Processor Technology

Publications

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  1. Published

    A new method for fast skeletonization of binary images on cellular processor arrays

    Wang, B., Mroszczyk, P. & Dudek, P., 2014, 14th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2014. IEEE

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    DOI: 10.1109/CNNA.2014.6888649
  2. Published

    A novel area-efficient binary adder

    Furber, S. B. & Liu, J., 2000, Conference Record of the Asilomar Conference on Signals, Systems and Computers. Vol. 1. p. 119-123 5 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  3. Published

    A Novel Framework for Utilising Multi-FPGAs in HPC Systems

    Pham, K. & Koch, D., 10 Sep 2019, Heterogeneous Computing Architectures: Challenges and Vision. Terzo, O., Djemame, K., Scionti, A. & Pezuela, C. (eds.). Taylor & Francis, p. 153-170 18 p.

    Research output: Chapter in Book/Report/Conference proceeding › Chapter

  4. Published

    A novel programmable parallel CRC circuit

    Grymel, M. & Furber, S. B., Oct 2011, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 10, p. 1898-1902 4 p., 5549980.

    Research output: Contribution to journal › Article › peer-review

    DOI: 10.1109/TVLSI.2010.2058872
  5. Published

    A partial reconfiguration controller for Altera Stratix V FPGAs

    Xiao, Z., Koch, D. & Lujan, M., 29 Aug 2016, 26th International Conference on Field Programmable Logic and Applications (FPL): FPL 2016. IEEE Computer Society , p. 1 4 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    DOI: 10.1109/FPL.2016.7577349
  6. Published

    A programmable adaptive router for a GALS parallel system

    Wu, J., Furber, S. & Garside, J., 2009, Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. USA: IEEE, p. 23-31 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    DOI: 10.1109/ASYNC.2009.17
  7. Published

    A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips

    Okuno, H., Kawasetsu, T., Plana, L. A., Furber, S. B. & Yagi, T., 22 Jan 2014, 2014 International Symposium on Artificial Life and Robotics (AROB 2014).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  8. Published

    A real-time, event-driven neuromorphic system for goal-directed attentional selection

    Galluppi, F., Brohan, K., Davidson, S., Serrano-Gotarredona, T., Carrasco, J. A. P., Linares-Barranco, B. & Furber, S., 2012, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 2 ed. Vol. 7664 LNCS. p. 226-233 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7664 LNCS, no. PART 2).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    DOI: 10.1007/978-3-642-34481-7_28
  9. Published

    A Robust Evolutionary Optimisation Approach for Parameterising a Neural Mass Model

    Zareian, E., Chen, J. & Sen Bhattacharya, B., Sep 2016, Artificial Neural Networks and Machine Learning – ICANN 2016: 25th International Conference on Artificial Neural Networks, Barcelona, Spain, September 6-9, 2016, Proceedings, Part II. Villa, A. E. P., Masulli, P. & Pons Rivero, A. J. (eds.). Switzerland: Springer Nature, p. 225-234 10 p. (Lecture Notes in Computer Science; vol. 9887).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    DOI: 10.1007/978-3-319-44781-0_27
  10. Published

    A Security Library for FPGA Interlays

    Vaishnav, A., Garcia Ordaz, J. R. & Koch, D., 5 Oct 2017, International Conference on Field Programmable Logic and Applications (FPL). Ghent, Belgium: IEEE

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    DOI: 10.23919/FPL.2017.8056817
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