Advanced Processor Technology

Publications

  1. 2019
  2. Accepted/In press

    Relating the Bisection Width of Dual-Port, Server-Centric Datacenter Networks and the Solution of Edge Isoperimetric Problems in Graphs

    Erickson, A., Navaridas, J. & Stewart, I. A., 15 Aug 2019, (Accepted/In press) In : Journal of Computer and System Sciences.

    Research output: Contribution to journalArticle

  3. Published

    SLAMBench 3.0: Systematic Automated Reproducible Evaluation of SLAM Systems for Robot Vision Challenges and Scene Understanding

    Bujanca, M., Gafton, P., Saeedi, S., Nisbet, A., Bodin, B., O'Boyle, M. F., Davison, A. J., Kelly, P. H., Riley, G., Lennox, B., Luján, M. & Furber, S., 12 Aug 2019, 2019 International Conference on Robotics and Automation (ICRA). Institute of Electrical and Electronics Engineers

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  4. Accepted/In press

    ZUCL2.0 Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs

    Pham, K., Paraskevas, K., Vaishnav, A., Attwood, A., Vesper, M. & Koch, D., 7 Aug 2019, (Accepted/In press) Sixth International Workshop on FPGAs for Software Programmers (FSP 2019). VDE Verlag

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  5. Accepted/In press

    First steps in porting the LFRic Weather and Climate model to the FPGAs of the EuroExa architecture

    Ashworth, M., Riley, G., Attwood, A. & Mawer, J., 31 Jul 2019, (Accepted/In press) In : Scientific Programming.

    Research output: Contribution to journalArticle

  6. Accepted/In press

    Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level

    Foutris, N., Kotselidis, C. & Luján, M., 22 Jul 2019, (Accepted/In press) 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Institute of Electrical and Electronics Engineers

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  7. Accepted/In press

    Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi

    Paredes Lopez, M., Riley, G. & Luján, M., 27 Jun 2019, (Accepted/In press) In : I E E E Transactions on Parallel and Distributed Systems.

    Research output: Contribution to journalArticle

  8. Published

    SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs

    Iordanou, K., Palomar, O., Mawer, J., Gorgovan, C., Nisbet, A. & Luján, M., 13 Jun 2019, IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Institute of Electrical and Electronics Engineers

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  9. Published

    Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures

    Vaishnav, A., Pham, K. & Koch, D., 6 Jun 2019, 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART). ACM Digital Library

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  10. Accepted/In press

    A Dynamic Adaptation Strategy for Energy-Efficient Keyframe-Based Visual SLAM

    Khalufa, A., Riley, G. & Luján, M., 5 Jun 2019, (Accepted/In press) The 25th International Conference on Parallel and Distributed Processing Techniques and Applications .

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  11. Accepted/In press

    The FOS (FPGA Operating System) Demo

    Vaishnav, A., Pham, K., Manev, K. & Koch, D., 22 May 2019, (Accepted/In press) 29th International Conference on Field Programmable Logic and Application (FPL). Barcelona, Spain

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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